<?xml version="1.0" encoding="utf-8" standalone="yes"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/">
  <channel>
    <title>CUDA on Chhaya&#39;s Space</title>
    <link>https://chkda.github.io/tags/cuda/</link>
    <description>Recent content in CUDA on Chhaya&#39;s Space</description>
    <image>
      <title>Chhaya&#39;s Space</title>
      <url>https://chkda.github.io/%3Clink%20or%20path%20of%20image%20for%20opengraph,%20twitter-cards%3E</url>
      <link>https://chkda.github.io/%3Clink%20or%20path%20of%20image%20for%20opengraph,%20twitter-cards%3E</link>
    </image>
    <generator>Hugo -- 0.163.3</generator>
    <language>en-us</language>
    <lastBuildDate>Sun, 05 Jul 2026 00:00:00 +0000</lastBuildDate>
    <atom:link href="https://chkda.github.io/tags/cuda/index.xml" rel="self" type="application/rss+xml" />
    <item>
      <title>GPU Internals: A Speed Run</title>
      <link>https://chkda.github.io/posts/gpu-internals-speed-run/</link>
      <pubDate>Sun, 05 Jul 2026 00:00:00 +0000</pubDate>
      <guid>https://chkda.github.io/posts/gpu-internals-speed-run/</guid>
      <description>&lt;p&gt;This article is mostly focussed on CUDA devices. From here onwards whenever I mention GPU know it to be CUDA by NVIDIA.&lt;/p&gt;
&lt;p&gt;All the notes that have been collected are for my self study. I will put sources below&lt;/p&gt;
&lt;h1 id=&#34;gpu-architecture&#34;&gt;GPU Architecture&lt;/h1&gt;
&lt;p&gt;CUDA stands for Compute Unified Device Architecture.&lt;/p&gt;
&lt;p&gt;&lt;img alt=&#34;GPU/CPU architecture&#34; loading=&#34;lazy&#34; src=&#34;https://chkda.github.io/images/gpu-internal-speed-run/CPU-GPU-Arch.svg&#34;&gt;&lt;/p&gt;
&lt;p&gt;&lt;em&gt;Figure adapted from the &lt;a href=&#34;https://modal.com/gpu-glossary/&#34;&gt;Modal GPU Glossary&lt;/a&gt;.&lt;/em&gt;&lt;/p&gt;
&lt;p&gt;GPU instructions are carried out by streaming multiprocessors (SMs).&lt;/p&gt;
&lt;p&gt;An SM in NVIDIA is analogous to a CPU core. SMs execute computation and store state for computation in registers and caches.&lt;/p&gt;</description>
    </item>
  </channel>
</rss>
